Typically, processors are constructed from a variety of very large scale integrated circuit (VLSI) chips used as building blocks in an architecture which can be divided into two subprocessors: an instruction processor that supervises the order and decoding of instructions to be executed, and a data processor which performs the operations called for by the instructions on the data. The instruction processor normally includes a microprogram memory which contains microinstructions. Each microinstruction includes a plurality of bits to control the elements within the data processor. In addition, a device or devices, termed a sequencer or microprogram controller, is used to issue addresses that are applied to the microprogram memory to access the microinstruction sequence to be executed. When processing conditional branching instructions, the sequencer, or microprogram controller, tests selected status bits of the data processor, such as overflow, zero, carry or negative.
Previous data processors have been categorized as either an 8, 16 or 32-bit device. They were capable of performing arithmetic or logic operations on 8, on 16, or on 32 bits, respectively. Some of these data processors have limited capability to perform operations on selected portions of a full-sized word. For example, a 16-bit data processor may be able to perform operations on the least-significant byte (8 bits) of a full-sized 16-bit word. In one such approach, a 16-bit processor is formed from a parallel combination of four four-bit processors. This is typically referred to as the "bit-sliced" technique.
This method, however, entails extensive parallel interconnection of the terminal pins of the data processor chips which can lead to malfunctioning and adds to the fabrication cost of the microprocessor. Furthermore, certain on-chip functions are needlessly duplicated, such as the microinstruction decode function present on each processor chip. Additionally, space, which is typically at a premium on the printed circuit boards used to mount the microprocessor chips, is consumed by a proliferation of data processor chips.
While previous 8- and 16-bit data processors have been available using bipolar semiconductor fabrication techniques, 32-bit data processors have been of the slower metal oxide silicon (MOS) type. Also contributing to speed degradation, previous processors used a single multiplexed input/output bus, which typically imposed a 50% duty cycle on input and output operation.
In modern data processing systems, data is continuously transferred between the host processor and its peripherals, storage, or terminals, such data often including coded control words that must be assembled or disassembled by the peripheral. Thus, packing or unpacking these coded data words, which may be binary-coded decimal (BCD) or American Standard Code of Information Exchange (ASCII) may be necessary. Typically, such packing and unpacking utilizes a rotation (i.e., a realignment of the bits of the coded word) and merge (logically ANDing the realigned coded word with a mask to pass only the desired bits and inhibit or strip away the unwanted bits) functions. Rotate and compare functions (similar to rotate and merge) are also widely used to compare a number of bits of a control or status data word with a predetermined unknown. These functions require complex programming and an inordinate amount of processing time.
Previous data processors have provided only limited support for these data manipulation features. Typically, masking, if available at all, was permitted on one operand only; and the mask was applied only to the entire word, or at best to some byte-aligned portion thereof. If only selected portions of the operands were to be arithmetically combined complex programming was required, degrading speed and needlessly adding instructions and temporary storage.
Further, errors may be introduced during the reading, writing or actual transmission of the data. Consequently, error control has become an integral part of the design of many of the peripheral units and their host computers. One of the more preferred methods today for error detection involves the addition of one or more bits, called "redundancy" bits, to the information carrying bits of a character or stream of characters. For example, one method commonly used for error detection is the simple parity check.
The speed of operation of the data processor, and therefore the microprocessor itself, depends in large part on the architecture of its internal circuitry. Throughput (the time it takes for an instruction to be executed) depends, in part, upon the number of gates data must pass through during its processing. Also, operating speed can be increased by combining several operations into one instruction. For example, certain high-speed processors available today provide a shift function to be performed with other arithmetic operations by placing a shifter on the output of the processor. Thus, an arithmetic operation and a shift (such as may be required in executing a multiplication-step instruction) can be performed in one instruction cycle, rather than two or more, and the operating speed of the microprocessor is thereby increased. However, the shift circuit, being on the output of the processor is always in the data path and, when not used, thereby increases the time it takes for the data to pass through the manipulation cycle; that is, overall throughput time is increased.
Another facet of the internal circuitry which degrades throughput is in the arithmetic carry circuit. Bottlenecks occur in previous processors because of the bit-by-bit carry propagation schemes used. Furthermore, these processors require large number of interconnections and use a very wide gate at the last stage of the carry circuitry. Also, previous processors require explicit normalization of the result of any floating-point multiplication or division. To do this, a series of normalization instructions would be executed; the number dependent on the particular operands being multiplied or divided.
Current data processors fall into one of the two incompatible types: those that employ carry during subtractions and those that employ borrow. No processor which works with either scheme is available, therefore requiring manufacture of each of the two types if one wants a processor compatbble with any existing microprocessor.
Another source of incompatibility of current data processors with extant hardware stems from the two types of on-chip parity checkers currently in use: even parity is utilized if compatibility with transistor-transistor logic (TTL) is desired, odd parity for emitter-coupled logic (ECL).